1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection for integrated circuits (ICs), and in particular, to low noise ESD protection for the analog inputs present on mixed signal (analog and digital) complementary metal oxide semiconductor (CMOS) integrated circuits. Digital switching noise, which is coupled into the analog inputs through the ESD protection circuitry, is dramatically reduced.
2. Description of the Related Art
FIGS. 1A and 1B show a simplified model for a conventional ESD protection circuit. For simplicity, only the two input/output (I/O) cells being "zapped" by the ESD event are shown. The circuit includes: two wires or nodes (esdPlus and esdMinus) which connect the circuit elements shown, two ESD protection diodes located inside each I/O cell (connected from the I/O cell pin to the esdPlus and esdMinus nodes), and an ESD switch which automatically closes during an ESD event. The two pins being zapped will be adequately protected during an ESD event if the peak voltage drop between them is less than the gate oxide breakdown voltage, BVox.
As shown in FIG. 1A, Pin 1 is being zapped positively with respect to Pin 2, so that diodes D1 and D4 are the only diodes conducting ESD current Izap. Conversely, in FIG. 1B, Pin 2 is being zapped positively with respect to Pin 1. In this case diodes D2 and D3 are the only diodes conducting ESD current Izap. In both examples the ESD current flows through the ESD switch (which closes only during an ESD event) in the same direction, independent of the polarity of the ESD event. Thus the ESD switch can be a unidirectional switch.
A simplified IC chip-level model for a conventional ESD protection circuit is shown in FIGS. 2 and 3. As shown in FIG. 3, this model includes: two concentric ESD rings (esdPlusRing and esdMinusRing) which encircle the periphery of the entire chip, passing through each I/O cell; two ESD protection diodes located inside each I/O cell (connected from the I/O pin to the two concentric ESD rings); and four ESD switches which automatically close during an ESD event, with one switch located in each corner of the chip.
As discussed above, ESD current will flow from the I/O pin being zapped positive to the I/O pin being zapped negative. As shown in FIGS. 2 and 3, this ESD current can flow through two ESD protection diodes, four corner switches and portions of the two ESD rings. The two pins being zapped will be adequately protected if the peak voltage drop between them (Vpin2pin) is less than the gate oxide breakdown voltage BVox. The value for the pin-to-pin voltage, Vpin2pin, can be computed using Equation (1). Equation 1 is based upon the simplified DC circuit model shown in FIG. 2. This simplified model yields a value for Vpin2pin which is normally within 10 to 20 percent of the value obtained from a transient ESD circuit simulation. EQU Vpin2pin=Izap*(2*Rfwd+Rh/2+Rv/4+Rs/4)+2*Vfwd (1)
where: ##EQU1##
It should be noted that FIG. 2 only shows the ESD circuitry for the two I/O pins which are being zapped. Thus the on-chip I/O circuitry which is also connected to these two I/O pins is not shown. In addition, the zapping circuit in FIG. 2 is represented by a current source Izap. This current source representation is sufficient because the value of Izap is almost entirely determined by the external zapping circuitry (i.e. the value of Izap is barely affected by the on-chip ESD protection circuitry).
A worst case ESD event occurs when the two pins being zapped are the furthest possible distance apart (i.e. diametrically opposed, on opposite sides of the chip). This produces the maximum IR (current times resistance) voltage drop in the ESD rings.
An example of an ESD corner switch is shown in FIG. 4. This corner switch employs an RC time constant (resistance times capacitance) to trigger an N-channel MOSFET, M1, which conducts approximately 1/4 of the total ESD current, Izap, as shown in FIG. 2. The resistance and capacitance values in FIG. 4 are chosen such that the RC time constant will be long in comparison to the duration of an ESD event (i.e. approximately 5-25 nanoseconds), but short in comparison to the rise time of the power supply voltage (which cannot be faster than 4 milliseconds for a 60 Hertz AC line). This restriction ensures that the switch will turn on during an ESD event, but will not turn on when the power supply voltage is initially applied. This type of ESD switch circuit is described in more detail in commonly assigned, co-pending U.S. patent application Ser. No. 09/005,197, filed Jan. 9, 1998, and entitled "Voltage Clamp Circuit for ESD Protection," the disclosure of which is hereby incorporated by reference. Further examples of other switch circuits suitable for use as ESD corner switches can be found in U.S. Pat. No. 5,239,440, entitled "Electrostatic Discharge Protection for Integrated Circuits," the disclosure of which is hereby incorporated by reference.
The use of dual ESD rings, as shown in FIGS. 2 and 3, is advantageous because it provides complete ESD protection for chips which have multiple, electrically isolated power supply pins and ground pins. This is particularly important for mixed signal CMOS chips, which often contain many separate (i.e. isolated) digital and analog supply pins, and digital and analog ground pins. Thus it should be understood that each of the pins being zapped in FIGS. 2 and 3 can be of any pin type (i.e. input, output, bi-directional, power supply and ground).
A major disadvantage of the circuit implementation shown in FIG. 3 is that it results in a high level of noise coupling between the digital circuit pins and the analog circuit pins. A simplified circuit model for this noise coupling is shown in FIG. 5. As shown in FIG. 5, the digital noise is generated by the on-chip digital output drivers and by the off-chip digital input drivers. This noise is AC-coupled onto the noise-sensitive analog input pins through the ESD protection rings (esdPlus and esdMinus). The digital noise is AC-coupled onto the ESD protection rings through the parasitic anode-to-cathode diode capacitances, C.sub.diode, which are associated with the ESD protection diodes.
Referring to FIG. 5, the parasitic wire capacitance C.sub.wire of the ESD rings (esdPlus and esdMinus) is generally much greater than the ESD diode capacitance C.sub.diode. However, when a number of digital drivers switch high or low at the same time, the relatively small diode capacitances C.sub.diode are then effectively connected in parallel to the same data (noise) source. For example, up to 48 digital output drivers can simultaneously change state on the PCI bus. In this case the multiple small diode capacitances C.sub.diode can act together as a single, but much larger, diode capacitance.
The amount of noise which is coupled into the analog inputs depends upon a number of circuit parameters. For example, the noise injected by the on-chip and off-chip digital signal drivers tends to increase as: 1) their output impedance decreases, 2) their output voltage swing increases, and 3) their rise and fall times decrease.
Susceptibility of the ESD rings (esdPlus and esdMinus) to injected noise depends upon whether they are left floating or are connected to a power supply line and a ground line. (Connection of esdPlus to more than one power supply line would violate the required isolation between power supply lines, while connection of esdMinus to more than one ground line would violate the required isolation between ground lines).
Susceptibility of the analog circuitry to injected noise tends to increase as the input impedance of the analog circuitry increases.
In order to prevent false triggering of the ESD protection circuitry during normal chip operation, the ESD rings (esdPlus and esdMinus) are usually not left floating. Thus esdPlus is normally connected to one power supply line, while esdMinus is normally connected to one ground line. Assuming that these connections have been made, noise injection into the analog circuitry will still not be completely eliminated. The main reasons for this are that: 1) the ESD rings have non-zero resistance, 2) the ESD rings are connected to power supply and ground pins which have non-zero inductance, and 3) the ESD rings are connected to a non-ideal power supply, i.e. a power supply which has a non-zero output impedance.